One-Fourth dimension Programmable

FPGA Fundamentals

R.C. Cofer , Benjamin F. Harding , in Rapid System Prototyping with FPGAs, 2006

two.1.5 FPGA Types

There are two broad categories of FPGA devices, reprogrammable and one-time programmable (OTP) devices. FPGA devices must exist programmed at some point in the blueprint process to define their functional operation. There are four different technologies for programming (configuring) FPGAs and they are detailed in Tabular array 2.5.

Table two.5.

Configuration Engineering Engineering Overview and Features
SRAM-based An external device (nonvolatile retention or µP) programs the device on ability up. Allows fast reconfiguration. Configuration is volatile. Device tin be reconfigured in-circuit.
Anti-Fuse-based Configuration is set by "called-for" internal fuses to implement the desired functionality. Configuration is nonvolatile and cannot be inverse.
EPROM-based Configuration is similar to EPROM devices. Configuration is nonvolatile. Device must be configured out of excursion (off-lath).
EEPROM-based Configuration is similar to EEPROM devices. Configuration is nonvolatile. Device must be configured and reconfigured out of circuit (off-board).

Configuring volatile FPGAs or SRAM FPGAs typically takes a few hundred milliseconds or less to complete. This time is mainly dependent on the size of the role, the configuration interface implemented and the speed of information transfer. However, the length of the configuration delay menstruum often is a modest consideration at the arrangement design level, when compared to the benefits of being able to dynamically reconfigure the FPGA in-circuit. This is especially the example when other types of devices, such as a processor, are present that likewise crave a kicking-up.

To configure an SRAM FPGA, the configuration data is usually loaded from an external nonvolatile configuration PROM, although FPGAs tin can also be configured direct by a processor or via a download cablevision from a PC. One-time programmable (OTP) devices, on the other hand, are fabricated upwards of traditional logic gates interconnected by employing anti-fuse technology. The connections between the gates are not "blown" but instead made into permanent connections. Therefore, OTP devices cannot be modified after they are programmed. OTP parts power up "configured" and thus take the reward of no configuration time or "instant on" functioning. Figure 2.ten illustrates an OTP FPGA implementation. The I1 block represents an input block, O1–O3 represent output blocks, and the white boxes within the FPGA correspond design logic and registers. Each of the filled boxes represents a permanent connectedness internal to the FPGA. These connection points define the signal routing and interface to logic and fixed-office blocks. Within a not-OTP component, these connections can be reconfigured, just are stock-still within an OTP component. OTP FPGA architecture details can exist plant in the Quicklogic and Actel family of data sheets.

Figure ii.x. OTP FPGA example

For rapid prototyping applications, the most critical FPGA technology feature is ease of function definition and re-definition. Typically, the function, content and implementation of the FPGA volition change numerous times over the life of the development and integration wheel. For this reason, the configuration technology selected must be reprogrammable rather than OTP. (Note that OTP FPGAs and non-ISP FPGAs may have significant applications within stable, well-tested products.)

SRAM-based FPGAs are oft the best design choice for prototyping and development projects. Due to the many advantages of developing designs with SRAM-based FPGAs, this book focuses on development with these devices. It is important to realize, however, that near all of the concepts and approaches presented inside this book also apply to OTP and non-Isp FPGA technologies.

The FPGA engineering science field has exhibited a turbulent history with many mergers, acquisitions and market departures. While at any given time there are a medium number of FPGA manufacturers, there are only a few manufacturers with significant sales and shipping designs. It is interesting to note that no major FPGA manufacturer owns their own fab; they are all fabless and rely on foundry partners to produce their silicon. Table 2.6 lists some of the largest electric current players in the FPGA market. The relative market shares of the top v vendors constantly fluctuate based on many factors. New families, devices, technologies and blueprint innovations are regularly announced. The data in this table is not comprehensive and may non list the full range of any company'south offering.

Table 2.vi.

Manufacturer Technology
Altera® SRAM, Flash
Actel Antifuse
Lattice SRAM, Wink
Quicklogic Antifuse
Xilinx SRAM

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The Fundamentals

Clive Max Maxfield , in FPGAs: Instant Access, 2008

—Engineering science Trade-offs—

•

Non surprisingly, devices based on antifuse technologies are OTP, because once an antifuse has been grown, it cannot be removed, and there'south no changing your mind.

•

Antifuse devices tend to be faster and crave lower power.

SRAM-based Engineering

There are 2 principal versions of semiconductor RAM devices: dynamic RAM (DRAM) and static RAM (SRAM). DRAM technology is of very piffling interest with regard to programmable logic, and then we will focus on SRAM.

Key Concept

SRAM is currently the dominant FPGA technology.

The "static" qualifier associated with SRAM means that—once a value has been loaded into an SRAM cell—it volition remain unchanged unless it is specifically altered or until ability is removed from the arrangement.

How It Works

Consider the symbol for an SRAM-based programmable jail cell ( Effigy 1-7 ).

Figure 1-7. An SRAM-based programmable cell.

The entire prison cell comprises a multitransistor SRAM storage element whose output drives an additional control transistor. Depending on the contents of the storage element (logic 0 or logic 1), the control transistor will be either OFF (disabled) or ON (enabled).

SRAM is currently the dominant FPGA technology.

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Configurable Computing

Wayne Luk , ... Nabeel Shirazi , in The Electrical Engineering Handbook, 2005

3.3.1 Run-Time Reconfigurable Devices

FPGAs, by definition, are configurable; nearly of them are also reconfigurable unless they are based on technologies such as Antifuse, that are sometime programmable. Several commercial devices back up partial reconfiguration, including the Virtex ( Xilinx, 2001) and 6200 (Churcher et al., 1995) devices from Xilinx, the CLAy chip from National Semiconductor (National Semiconductor, 1993), and the AT 40 K devices from Ateml (Atmel, 1997). Useful reviews of FPGA architectures are bachelor (Buell et al., 1996; Hauck, 1998; Kean, 2000; Mangione-Smith, 1997; Trumberger, 1994; Villasenor and Hutchings, 1998). Although some devices such every bit Xilinx 6200 FPGAs are no longer supported commercially, the ideas in the relevant publications may all the same inspire time to come advances.

A simple FPGA model is shown in Effigy 3.3. In this figure, processing elements, typically containing configurable logic and storage blocks, are represented by squares. The processing elements are connected to configurable switches, represented every bit circles, that command information flow by establishing the desired connectivity between the busses. Much of the expanse in an FPGA is usually taken up past the configurable switches and the busses; local and global busses can besides be organized hierarchically. The figure demonstrates the regularity constitute in most FPGAs; practical FPGAs frequently comprise additional resources, such equally configurable retentivity blocks and special-purpose input/output blocks supporting purlieus-scan testing (Trimberger, 1994).

FIGURE iii.3. A Simple Model of an FPGA. Squares represent configurable processing elements, and circles represent configurable switches to control routing.

Many experimental FPGA architectures support run-time reconfiguration. Tau et al., (1995) have come up up with an FPGA that stores multiple configurations in memory banks. In a single clock bicycle, which is in the order of tens or hundreds of nanoseconds, the chip can supplant configuration by another without erasing partially processed data.

A similar FPGA that can perform a context switch in i wheel has been developed by Trimberger et al. (1997). The FPGA tin store up to viii configurations in on-chip memory.

This FPGA is based on a Xilinx 4000E device and includes extensions for dealing with saving country from one context to another.

The Colt Group led past Athanas is investigating a run-time reconfiguration technique chosen Wormhole that lends itself to distributed processing (Bittner and Athanas, 1997). The unit of computing is a stream of data that creates custom logic as it moves through the reconfigurable hardware.

Schmit et al. (2000) have adult a reconfigurable FPGA targeted toward pipelined designs. Reconfiguration is performed at the level of individual pipeline stages, like to that described in Effigy three.ii. Others have shown that commercial partially reconfigurable FPGAs can also back up efficient reconfiguration of pipelined designs (Luk et al., 1997).

There are likewise configurable devices based on coarse-grain programmable elements (Conquist et al., 1998), multiple-bit arithmetic units (Marshall et al., 1999), and low-ability techniques (Rabaey, 1997). Kean (2000) provides an overview of commercial devices bachelor in the twelvemonth 2000.

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Field-Programmable Logic

In Top-Down Digital VLSI Design, 2015

2.2.three Antifuses

Fuses, which were used in earlier bipolar PROMs and SPLDs, are narrow bridges of conducting material that blow in a controlled way when a programming current is forced through. Antifuses, such as those employed in today's FPGAs, are thin dielectrics separating two conducting layers that are fabricated to rupture upon applying a programming voltage, thereby establishing a conductive path of low impedance.

In either example, programming is permanent. Whether this is desirable or not depends on the appli- cation. Total factory testing prior to programming of one-time programmable links is impossible for obvious reasons. Special circuitry is incorporated to test the logic devices and routing tracks at the manufacturer before the unprogrammed devices are being shipped. On the other hand, antifuses are simply about the size of a contact or via and, therefore, allow for higher densities than repro- grammable links, see fig.2.4c and d. Antifuse-based FPL is likewise less sensitive to radiation furnishings, offers superior protection against unauthorized cloning, and does non need to be configured following power-up.

Tabular array 2.one. FPL configuration technologies compared

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Debugging Components

Joseph Yiu , in The Definitive Guide to the ARM Cortex-M3 (2d Edition), 2010

16.6.two Flash Patch Feature

The Flash Patch office allows using a small programmable memory in the organization to utilize patches to a plan memory which cannot exist modified. For products to exist produced in high book, using mask ROM or one-time-programmable ROM can reduce the cost of the product. Merely, if a software bug is found later the device is programmed, information technology could exist costly to replace the devices. Past integrating a small reprogrammable memory, for instance, a very small Flash or Electrically Erasable Programmable Read Just Memory (EEPROM), patches can be fabricated to the original software programmed in the device. For microcontrollers that merely utilise Flash to store software, Flash Patch is non required as the whole Flash can be erased and reprogrammed easily.

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Foreword

Dan Butler , in Programming viii-bit Pic Microcontrollers in C, 2008

A decade ago, at that place were pregnant barriers to learning how to use microcontrollers. The cheapest developer was about a hundred dollars and application development required both erasable windowed parts—which price about ten times the toll of the in one case programmable (OTP) version—and a UV Eraser to erase the windowed office. Debugging tools were the realm of professionals alone. Now most microcontrollers use Flash-based program memory that is electrically erasable. This means the device tin be reprogrammed in the excursion—no UV eraser required and no special packages needed for development. The total toll to get started today is most twenty-five dollars which buys a PICkit™ 2 Starter Kit, providing programming and debugging for many Microchip Technology Inc. MCUs. Microchip Technology has always offered a gratis Integrated Development Environment (IDE) including an assembler and a simulator. It has never been less expensive to get started with embedded microcontrollers than it is today.

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Electronics Supply Chain

Swarup Bhunia , Mark Tehranipoor , in Hardware Security, 2019

half dozen.6.7 ECID and PUF-Based Authentication

ECID and PUF-based authentication approaches take been proposed to identify remarked and cloned ICs. The main thought here is to tag ICs with unique IDs, and track them throughout the supply chain. The electronic-chip-ID-based (ECID-based) approaches rely on writing the unique ID into a nonprogrammable memory, such every bit 1-Time-Programmable [OTP] and ROM. This requires post-fabrication external programming, such as light amplification by stimulated emission of radiation fuses [80] or electrical fuses (eFuses) [81]. The eFuse is gaining popularity over the laser fuse because of its small area and scalability [81].

Aslope ECID, silicon physically unclonable functions (PUFs) have received much attention as a new approach for IC identification and authentication [82,83]. Silicon PUFs exploit inherent physical variations (process variations) that exist in mod integrated circuits. These variations are uncontrollable and unpredictable, making PUFs suitable for IC identification and hallmark [28,84]. The variations can help generate a unique signature for each IC in a claiming-response grade, which allows subsequently identification of genuine ICs.

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Introducing the PIC mid-range family and the 16F84A

Tim Wilmshurst , in Designing Embedded Systems with Moving-picture show Microcontrollers (Second Edition), 2010

2.3 A review of retentivity technologies

In club to examine the memory capabilities of the 16F84A, and to work with embedded systems in general, it is important to have some cognition of the characteristics of the memory technologies in utilize. A detailed survey can be constitute in Chapter four of Ref. 1.i. The post-obit department gives merely a cursory overview of the different memory technologies currently used by Microchip.

An ideal memory reads and writes in negligible time, retains its stored value indefinitely, occupies negligible space and consumes negligible power. In exercise no retentivity technology meets all these happy ideals! In general, unlike technologies are strong in 1 or more than of these characteristics and weaker in others. There is not i best memory technology, and different technologies are therefore applied for different applications, according to their needs.

Whatever memory is made upwards of an 'array' of memory 'cells', where each cell holds one bit of data. The characteristics of the single cell reflect the characteristics of the overall array; therefore, each technology is described here merely in terms of its cell design.

2.3.1 Static RAM (SRAM)

Here each retentivity cell is designed as a simple flip-flop, using ii pairs of transistors connected back-to-back. Two further transistors allow the cell to connect into the main assortment. Data is held only every bit long as power is supplied. Hence the SRAM applied science is volatile. With each cell taking six transistors, SRAM is not a loftier-density applied science. However, if made from CMOS (Complementary Metal Oxide Semiconductor) it can be made to eat very little ability, and can retain its data downwardly to a low voltage (effectually 2 5). It has thus been a popular technology in battery-powered systems. SRAM is mainly used for data memory (RAM) in a microcontroller.

2.iii.2 EPROM (Erasable Programmable Read-Only Memory)

In this applied science each retentiveness jail cell is made of a unmarried MOS transistor – but with a difference. Within the transistor there is embedded a 'floating gate'. Using a technique known as hot electron injection (HEI), the floating gate tin can be charged. When it is not charged, the transistor behaves commonly and the cell output takes ane logic country when activated. When it is charged, the transistor no longer works properly and it no longer responds when it is activated. The charge placed on the floating gate is totally trapped by the surrounding insulator. Hence EPROM applied science is not-volatile. EPROM can, withal, exist erased by exposing it to intense ultraviolet light. This gives the trapped electrons the energy to get out the floating gate.

A special version of EPROM is OTP (One Fourth dimension Programmable). Here the EPROM is packaged in plastic, without a window. Therefore, OTP tin be programmed but once and never erased.

With a single transistor for a jail cell, EPROM is very high density and robust. Its requirement of a quartz window and ceramic packaging, to enable erasing, raises its cost and reduces its flexibility. EPROM used to exist integrated onto many microcontrollers for plan memory, forcing the whole microcontroller to be ceramic-packaged with a quartz window (as seen in Figure i.10). As a technology, EPROM has now almost completely given style to Flash, which follows soon, but y'all may come beyond it in older systems.

ii.3.3 EEPROM (Electrically Erasable Programmable Read-Only Memory)

EEPROM also uses floating gate applied science. Its dimensions are finer, and then that it tin can exploit some other means of charging its floating gate. This is known as Nordheim–Fowler tunnelling (NFT). With NFT, it is possible to electrically erase the retentiveness prison cell as well as write to information technology. To permit this to happen, a number of switching transistors need to be included effectually the retentiveness element itself, so the loftier density of EPROM is lost.

Generally, EEPROM tin exist written to and erased on a byte-by-byte basis. This makes information technology especially useful for storing single items of data, like television settings or mobile phone numbers. Both writing and erasing take finite fourth dimension, upwardly to several milliseconds, although a read can exist accomplished at normal semiconductor memory access times, i.e. within microseconds or less. Again, like EPROM, because the charge on the floating gate is totally trapped by the surrounding insulator, EEPROM is non-volatile. Because the EEPROM construction is now so fine, it suffers from sure wear-out mechanisms. Manufacturers commonly therefore define a guaranteed minimum number of erase/write cycles that their retention can successfully undergo.

two.3.4 Flash

Flash represents a farther evolution of floating-gate engineering. With a single transistor per memory cell, information technology uses both HEI and NFT to allow electrical writing and erasing. It does not include the extra switch transistors that EEPROM has, so can just erase in blocks. It therefore returns to the exceptionally loftier density of EPROM. Like EEPROM, information technology has wear-out mechanisms, so cannot exist written and erased indefinitely.

Apart from its inability to erase byte-by-byte, Flash is an incredibly powerful technology. It is now a central characteristic of a huge range of products, including digital cameras, 'memory sticks', laptop computers and microcontroller program memory.

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Programmable logic devices

B. HOLDSWORTH BSc (Eng), MSc, FIEE , R.C. Wood MA, DPhil , in Digital Logic Design (Quaternary Edition), 2002

xi.2 Read only memory

A read only memory (ROM) scrap in its most basic form stores a big number of binary integers, 1 at each unique value of the ROM address which acts in the same way every bit a 'firm number' and identifies each stored integer or binary discussion by its memory location. When the external logic arrangement presents an accost or retention location to the ROM, the ROM returns the data stored in the annals or memory storage at that address. Each register is capable of storing one binary integer, originally placed there either past the flake manufacturer working from data supplied by the logic arrangement designer, or by the arrangement designer taking the ROM chip through a special programming process. A typical ROM consists of an array of addressable registers of identical length (number of bits); each register or 'memory location' has a unique address (a binary integer in the range 0 to 1 fewer than the total number of locations) and can be selected past circuitry included in the ROM designed to read and translate the address number required (similar to an address decoder equally described in Chapter 5). A cake diagram showing the basic components of a typical ROM is shown in Figure 11.one. The ROM has north accost lines and, since there are 2 n possible combinations of due north binary digits, the chip will house 2 n registers. Each register is identified or addressed past one of the 2 n output lines of the internal address decoder contained within the ROM chip.

Effigy eleven.1. The internal cake structure of a ROM

In the ROM shown in Figure 11.ane, each register contains p $.25, and and then the full storage capacity of the ROM is p × 2 due north bits. For a typical discussion length p = 8 and a typical number of address lines due north = 12, the total storage chapters is 8 × 212 = 32768 bits. A grouping of eight binary digits is often referred to as a byte, so that the storage capacity of this particular ROM is ii12 = 4096 bytes, or 4K byte, where K means 1024 and is pronounced 'kilo' by analogy with the usual measurement unit prefix. This memory scrap may also be described as a 4K × 8 ROM, or as a 4K byte-organised ROM.

When a ROM is incorporated into a digital system where communication between devices is via an interconnecting bus organisation, two command signals are normally required. In many applications, for example a microprocessor system, where a number of ROMs may be used to store a program, only one ROM must be continued to the motorbus arrangement at any given instant. The ROM to exist continued to the motorbus will exist identified past activating its scrap select (CS) bespeak. Additionally, the ROMs may exist connected to the bus system via tri-land gates which are in the high impedance state until they are enabled by an output enable (OE) signal. Once enabled, the data at the input to the tri-state buffers will be transferred to the bus.

Estimator systems also apply large numbers of random access retention (RAM) chips to store temporary results of computations and processing. There are two main types of RAM: static RAM, in which each scrap of information is stored on the equivalent of a single D-type flip-flop, and dynamic RAM, in which each chip of information is stored as an electric charge on the gate capacitor of a MOSFET. Since the capacitors are not perfect and the charge leaks away afterwards 1ms or and so, the charge must be 'refreshed' regularly. The advantage of static RAM is that refreshing is not needed, whereas the advantage of dynamic RAM is that the 'packing density' (number of stored bits per flake) of bachelor devices is much greater than on available static RAM devices. RAM chips accept an internal structure similar to ROM chips except that information can exist stored an unlimited number of times in any or all of the memory locations. This information is generally lost when power is removed from the RAM chip, that is, the data is, said to be 'volatile', although special 'non-volatile' RAM chips are also available. Therefore, a RAM needs a tertiary control signal, the write (WR) r e a d ¯ ( R D ¯ ) signal. If WR is activated simultaneously with CS, data is transferred from the RAM data lines to the internal data register selected. However, if WR is not activated and so the RAM behaves similarly to a ROM chip. Autonomously from this extra indicate, RAM circuitry is in principle like to ROM circuitry, except that to be useful RAM must kickoff take data stored in it and this limits its utilize about exclusively to reckoner and microprocessor systems which are outside the scope of this text.

ROMs are, by definition, non-volatile memories because the programme written into the retentiveness, when it is initially programmed, remains stored when the power is removed. Because of its non-volatility, ROM is typically used for basic program storage and too for the storage of unchanging data patterns.

There are several main categories of ROMs currently available:

i.

Mask programmed by manufacturer. The data stored in the ROM, the 'contents', are programmed by the manufacturer during fabrication according to a specification supplied by the customer. This type of ROM is but suitable when the designer'south required data or programme has been extensively tested and verified to avoid errors, every bit it is non possible to modify the stored information afterward fabrication and packaging. Programming these devices during manufacture requires expensive equipment and is economic only for very loftier book applications and, in improver, there may be some delays before the final devices are produced.

two.

PROMs (Programmable ROMs ). The PROM contents are written into the PROM by the user with the assistance of a slice of equipment known as a 'PROM developer'. Programming this type of ROM is essentially an irreversible procedure, and so this blazon is sometimes referred to every bit 'Old programmable' (OTP). Since PROMs are relatively cheap, they are often used in the early on stages of product evolution when considerable changes may have to be made to the stored program, every bit the changes can be made past simply programming another PROM by the user. When the design has been finalised, the data may be sent to a ROM manufacturer for mass product of a high-volume mask-programmed ROM dedicated to the proven design. Alternatively, low-book applications can continue to use individually programmed PROMs.

iii.

EPROMs (Erasable PROMs). The contents are programmed electrically by the user but can be subsequently erased, followed past loading new programming data. This is accomplished by shining Ultra-Violet (UV) light, from a special UV source designed for EPROM erasure, for a menstruum of ten to twenty minutes through a transparent window on tiptop of the ROM package. This type of ROM may therefore be recognised past the presence of this window, usually around 10 mm × x mm, through which the actual ROM fleck may be seen. Similar PROMs, EPROMs can be used for system development as well as for low-volume production, in which example it is normal to embrace the window with opaque tape to prevent inadvertent erasure of the EPROM contents. Frequently the manufacturers state a limit of maybe 100 UV erasures that can exist undertaken with any one EPROM before the erasure and storage become unreliable.

four.

EEPROMs (Electrically Erasable Programmable ROMs). This type of user-programmable ROM can accept its program completely erased electrically. However, in that location is a limit to the number of times that the stored data can be erased and the device reliably reprogrammed, and then EEPROMs are not a substitute for 18-carat RAM.

A typical example of an EPROM is the TMS27128 containing 131072 bits (16Kbyte). Before programming, the scrap is erased by UV radiations (then that all bits are set to one), and after erasure, 0s are programmed in those locations specified past the designer. The TMS27128 EPROM is packaged every bit a 28-pin IC; farther increase in storage capacity (with the same control facilities) requires an IC having more 28 pins. The TMS47256 ROM has a storage capacity of 262144 bits (32Kbyte) just with simpler control facilities fabricated every bit a 28-pivot IC. The Appendix on Functional Logic Symbols describes in detail the symbols for these devices.

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Selecting a design road

John Crowe , Barrie Hayes-Gill , in Introduction to Digital Electronics, 1998

11.iv.half dozen CAD tools for field programmable logic

The programming of field programmable logic devices is implemented directly via a computer. The software needed for PALs and PLAs is commonly a uncomplicated matter of producing a programming file called a fuse or an EPROM chip file. This file has a standard format (called JEDEC) and contains a list of l's and O's. This file is automatically generated from either Boolean equations, truth tables or state diagrams using programs such as ABEL (DatalO Corp.), PALASM (AMD Inc.) and CUPL (Logical Devices Inc.). In other words the minimisation is done for you and information technology is not necessary to describe out any Karnaugh maps. Software programs that can directly convert a schematic representation into a JEDEC file are also available. Since these devices take but an MSI complexity level then the software tools are relatively simple to utilize and also cheap.

The FPGAs, on the other hand, take capacities of LSI and VLSI level and are much more complex. Since FPGAs are similar in nature to mask programmable gate arrays the associated CAD tools accept been derived from mask programmable ASICs and follow that of Fig. xi.13; that is: schematic capture (or VHDL), prelayout simulation, layout, back notation and postlayout simulation.

It should be noted that FPGA simulation philosophy is somewhat different from mask programmable gate arrays. With mask programmable devices, 100% simulation is absolutely essential since these circuits cannot exist rectified after fabrication without incurring large financial and time penalties. These penalties are virtually eliminated with FPGA engineering due to the fast programming time in the laboratory and the low cost of devices. For one-fourth dimension programmable devices (such as Actel) the penalty is the price of one chip whilst for erasable devices (such as Xilinx) the devices can just be reprogrammed. Hence the pressure level to simulate 100% is not every bit great.

For those devices that are reprogrammable this results in an inexpensive iterative procedure whereby a device is programmed and and then tested in the final arrangement. If the device fails it can exist reprogrammed with the mistake corrected. For OTP type FPGAs then a new device will have to be blown at each iteration; although it volition incur a small charge the cost is considerably less than mask programmable arrays. It is non uncommon for FPGA designs (both reprogrammable and OTP) to feel iv iterations before a working device is obtained. This is totally unthinkable for mask programmable designs where a 'right first time approach' has to be employed - hence the reliance on the simulator.

Since fuses, SRAM/MUX cells, etc., are used to control the connectivity the delays acquired by these elements must be added to the wire delays for postlayout simulation. Hence it is for this reason that FPGAs operate at a lower frequency than mask programmable gate arrays. The large delays in the routing path also mean that timing characteristics are routing dependent. Hence, changing the placement positions of core cells (by altering the pivot out for instance) will upshot in a different timing performance. If the blueprint is synchronous then this should not be a problem with the exception of the shift register trouble referred to in Figure. 11.14. It should also be noted that the prelayout simulation of FPGAs on some occasions is only a unit of measurement filibuster (i.e. 1 ns for all gates) or functional simulation. It does not take into business relationship fan-out, individual gate delays, set-upwards and hold time, minimum clock pulse widths (i.e. spike and glitch detector), etc., and does not make whatever estimate of the wire delay. Hence the simulation at this stage is not reflective of how the last design will perform. To obtain the true delays the FPGA must exist laid out and the delays back annotated for a postlayout simulation. This volition provide an accurate simulation and hence reveal any design errors. Unfortunately, if a mistake is institute so the designer must return all the way back to the original schematic. The pattern must again be prelayout simulated, laid out and delays back annotated earlier the postlayout simulation can be repeated. This tedious iterative procedure is another reason why FPGAs are ordinarily programmed prematurely with a express simulation. Information technology should be mentioned that an FPGA is sometimes used as a prototyping route prior to migrating to a mask programmable ASIC. Hence the do of postlayout simulation using back annotated delays is an important discipline for an engineer to larn in preparation for moving to mask programmable ASICs.

When all the CAD stages are completed the FPGA internet-listing file is converted into a programming file to plan the device. This is either a standard EPROM chip file for the Xilinx and Altera arrays or a fuse file for the Actel devices. In one case a device is programmed, debug and diagnostic facilities are available. These permit the logic country of any node in the circuit to be investigated after a series of signals has been passed to the chip via the PC serial or parallel port. This feature is unique to FPGAs since each node is addressable dissimilar mask programmable devices.

FPGA CAD tools are normally divided into two parts. The first is the prelayout phase or front-end software, i.e. schematic and prelayout simulation. The CAD tools hither are generic (suitable for any FPGA) and are provided by proprietary packages such as Mentor Graphics, Cadence, Viewlogic, Orcad, etc. However, to access the FPGAs the corresponding libraries are required for schematic symbols and models.

The 2nd part is chosen the back-end software incorporating: layout; back notation of routing delays; programming file generation and debug. The software for this part is usually tied to a particular type of FPGA and is supplied by the FPGA manufacturer.

For case consider a typical CAD route with Actel on a PC. The prelayout (or front end stop) tools supplied by Viewlogic tin be used to depict the schematic using a package called Viewdraw and the prelayout functional simulation is performed with Viewsim. In both cases library files are needed for the desired FPGA. One time the pattern is correct it can be converted into an Actel net-list using a internet-list translator. This new file is and so passed into the CAD tools supplied by Actel (called Actel Logic System - ALS) ready for place and routing. The parasitic delays tin can be extracted and back annotated out of ALS back into Viewlogic so that a post-layout simulation tin can be performed over again with Viewsim. If the simulation is not correct then the circuit schematic must exist modified and the array is placed and routed once more. Actel provide a static timer to bank check ready-up and concur time and summate the delays downwards all wires indicating which wire is the heaviest loaded. A useful facility is the net criticality assignment which allows nets to be tagged depending on how speed critical they are. This facility controls the placing and routing of the logic in lodge to minimise wiring delays wherever possible. The device is finally programmed by starting time creating a fuse file and then blowing the fuses via a slice of hardware called an activator. This connects to an Actel programming menu inside the PC. Every bit an example of the length of time the place and route software tin can have to complete the authors ran a design for a 68 pin Actel 1020 device. The layout process took approximately 10 minutes using a 486, 66 MHz PC and utilised 514 (approximately 1200 gates) of the 547 modules available (i.e. a utilisation of 94%). In addition on the same figurer the fuse programming via the activator took around 1 minute to complete its program. With mask programmable ASICs, however, the programming step tin can accept at least four weeks to consummate! This is one of the great advantages that FPGAs have over mask programmable ASICs. Note, however, that equally with mask programmable arrays the FPGA manufacturers but provide a limited range of array sizes. The final pattern thus never ever uses all of the gates available and hence silicon is wasted. Also, equally the gates are used upwards on the array the ability for the router to access the remaining gates decreases and hence although a manufacturer may quote a maximum gate count for the assortment the important figure is the percentage utilisation.

Actel FPGAs as well accept comprehensive postprogramming examination facilities bachelor under the choice 'Debug'. These consist of: the functional debug selection; and the in-circuit diagnostic tool. The functional debug examination involves sending test vectors from the PC to the activator, which houses the FPGA during programming, and simple tests can be carried out. The in-circuit diagnostic tool is used to cheque the existent time functioning of the device when in the final PCB. This examination is 100% appreciable in that whatsoever node inside the chip tin can be monitored in real fourth dimension with an oscilloscope via two dedicated pins on the FPGA.

The Xilinx FPGA devices are programmed in a like fashion by using two pieces of software. Again typical front-end software for these devices is Viewlogic utilising Viewdraw and Viewsim for excursion entry and functional simulation respectively. The net-list for the schematic is this time converted into a Xilinx internet-list and the design tin now move into the Xilinx evolution software supplied by Xilinx (called XACT). Although individual programs exist for place and road, parasitic extract, programming file generation, etc., Xilinx provide a elementary to use compilation utility chosen XMAKE. This runs all of these steps in one process. Parasitic delays can again exist back annotated to Viewsim for a timing simulation with parasitics included. A static timing analyser is again available so that the effects of delays can exist observed on ready-up and agree time without having to utilize input stimuli. Fleck stream configuration data, used in conjunction with a Xilinx provided cable, allow the data to exist down-loaded to the chip for configuration. As with Actel both debug and diagnostic software exist such that the device tin exist tested and any node in the excursion monitored in real fourth dimension. The chip stream data tin exist converted into either Intel (MCS-86), Motorola (EXORMAX) or Tektronix (TEKHEX) PROM file formats for subsequent PROM or EPROM programming. The one disadvantage of these devices as compared to the Actel devices is that when in last use the device needs to have an associated PROM or EPROM which increases the component count.

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